1. Field of the Invention
The present invention relates to a computer program product, system, and method for selecting Direct Memory Access engines in an adaptor for processing Input/Output requests received at the adaptor.
2. Description of the Related Art
In a dual cluster system, each cluster includes a processing complex and cache. Each cluster is assigned a plurality of volumes, where volumes may be grouped in Logical Subsystems (LSSs). Data being written to a volume may be stored in the cache of the cluster to which the data is assigned. Multiple clusters may receive I/O requests from hosts over a network via a shared network adaptor in the storage controller including the dual clusters.
The shared network adaptor may include a plurality of ports on which I/O requests are received, a plurality of DMA engines to transfer data between the clusters and the ports on which the I/O requests are received, and a plurality of processors (or cores on a single central processing unit) to process I/O requests and control the DMA engines to transfer data for the I/O requests. A processor may be assigned or have affinity for particular ports, so only one processor processes the I/O requests for a port and returns complete or data to the assigned port on which the I/O request was initiated. The DMA engines may have affinity or be assigned to particular logical subsystems (LSSs) or volumes, such that the LSS or volume including the target data of the I/O request is used to determine the DMA engine in the adaptor to use to handle the data transfer to or from the clusters.
Each DMA engine includes a completion queue in which the DMA engine queues completes when completing the data transfer to or from the cluster. Any processor can access any of the DMA engines to process the I/O completes in their completion queues when that processor is scheduled to check I/O completes at the DMA engines. The processor adds the I/O complete pulled from the DMA engine completion queue to a port queue in memory specific to the port that received the I/O request subject to the I/O completion. The processor processes I/O completes in the port queues of ports assigned to the processor. However, if the port queue for the port to which the I/O complete relates is empty, then the processor directly processes the I/O complete to return data or acknowledgment on the port to which the I/O complete relates, without queuing that I/O complete on the port queue.
There is a need in the art for improved techniques for selecting DMA engines to use in a network adaptor.